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general description the max1363/max1364 low-power, 12-bit, 4-channelanalog-to-digital converters (adcs) feature a digitally programmable window comparator with an interrupt out- put for automatic system-monitoring applications. once configured, monitor mode automatically asserts an inter- rupt when any analog input exceeds the programmed upper or lower thresholds, without interaction to the host. the max1363/max1364 respond to the smbus alert, allowing quick identification of the alarming device on a shared interrupt. a programmable delay between monitoring intervals lowers power consumption for reduced monitoring rates. in addition, the max1363/max1364 integrate an inter- nal voltage reference, a clock, and a 1.7mhz, high- speed, i 2 c-compatible, 2-wire serial interface. the opti- mized interface allows a maximum conversion rate of94.4ksps in normal mode while reading back the con- version results. each of the four analog inputs is config- urable for single-ended or fully differential operation and unipolar or bipolar operation. two scan modes uti- lize on-chip random access memory (ram) to allow eight conversions of a selected channel or scanning of a group of channels to reduce interface overhead. these devices operate from a single 2.7v to 3.6v (max1363) or 4.5v to 5.5v (max1364) supply and require only 436? at the maximum sampling rate of 133ksps in monitor mode and 670? at the maximum sampling rate of 94.4ksps. autoshutdown powers down the devices between conversions, reducing sup- ply current to less than 1? when idle. the full-scale analog-input range is determined by the internal reference or by an externally applied reference voltage ranging from 1v to v dd . the max1363 features a 2.048v internal reference, and the max1364 featuresa 4.096v internal reference. the max1363/max1364 are available in a 10-pin ?ax package and are specified over the extended (-40? to +85?) temperature range. for 10-bit applica-tions, refer to the pin-compatible max1361/max1362 data sheet. applications system monitoring/supervisionservers/workstations high-reliability power supplies medical instrumentation features ? monitor mode programmable lower/upper trip thresholdalarm-status register records fault events smbus alert response programmable sampling intervals ? 12-bit, i 2 c-compatible adc ? lsb inl, ? lsb dnl ? 4-channel single-ended or 2-channel fullydifferential inputs ? software-programmable bipolar/unipolarconversions ? fast sampling rate 94.4ksps while continuously readingconversions 133ksps in monitor mode ? high-speed, i 2 c-compatible serial interface 100khz/400khz standard/fast modeup to 1.7mhz high-speed mode six available i 2 c slave addresses ? single supply 2.7v to 3.6v (max1363)4.5v to 5.5v (max1364) ? internal reference 2.048v (max1363)4.096v (max1364) ? external reference: 1v to v dd ? low power 436? in monitor mode (133ksps)670? at 94.4ksps 6? at 1ksps 0.5? in power-down mode ? small package 10-pin ?ax max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-3338; rev 3; 3/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package i 2 c slave address supply voltage (v) max1363 eub+ -40? to +85? 10 ?ax 0110100/0110101 2.7 to 3.6 MAX1363MEUB+ -40? to +85? 10 ?ax 0110110/0110111 2.7 to 3.6 smbus is a trademark of intel corporation. autoshutdown is a trademark of maxim integrated products, inc. ?ax is a registered trademark of maxim integrated products, inc. typical operating circuit and pin configuration appear at end of data sheet. ordering information/selector guide continued at end of data sheet. +denotes a lead-free package. downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus aler t response 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = 2.7v to 3.6v (max1363), v dd = 4.5v to 5.5v (max1364), v ref = 2.048v (max1363), v ref = 4.096v (max1364), c ref = 0.1?, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ain0?in3, a0, ref to gnd......................-0.3v to (v dd + 0.3v) sda, scl, int to gnd .............................................-0.3v to +6v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 10-pin ?ax (derate 5.6mw/? above +70?) ........444.4mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy (f sample = 94.4ksps) (note 1) resolution 12 bits relative accuracy inl (note 2) ? lsb differential nonlinearity dnl no missing codes ? lsb offset error ? lsb offset-error temperaturecoefficient relative to fsr 0.3 ppm/ c gain error (note 3) ? lsb gain temperature coefficient relative to fsr 0.3 ppm/ c channel-to-channel offsetmatching ?.1 lsb channel-to-channel gainmatching ?.1 lsb dynamic performance (f in(sine-wave) = 10khz, v in(p-p) = v ref , f sample = 94.4ksps) signal-to-noise plus distortion sinad 70 db total harmonic distortion thd up to the 5th harmonic -78 db spurious-free dynamic range sfdr 78 db full-power bandwidth sinad > 57db 3.0 mhz full-linear bandwidth -3db point 5.0 mhz conversion rate internal clock 7.5 conversion time (note 4) t conv external clock 10.6 ? internal clock, scan[1:0] = 01 51 external clock 94.4 throughput rate (note 5) f sample monitor mode, scan[1:0] = 10 133 ksps downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = 2.7v to 3.6v (max1363), v dd = 4.5v to 5.5v (max1364), v ref = 2.048v (max1363), v ref = 4.096v (max1364), c ref = 0.1?, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units track/hold acquisition time 800 ns internal clock frequency 2.8 mhz external clock, fast mode 60 aperture delay (note 6) t ad external clock, high-speed mode 30 ns analog input (ain0?in3) unipolar 0 v ref input voltage range, singleended and differential (note 7) bipolar -v ref / 2 +v ref / 2 v input multiplexer leakage current on/off-leakage current, v ain_ = 0 or v dd ?.01 ? ? input capacitance c in 22 pf internal reference (note 8) max1363 2.027 2.048 2.068 reference voltage v ref t a = +25? max1364 4.055 4.096 4.137 v reference-voltage temperaturecoefficient tcv ref 25 ppm/? ref short-circuit current 2m a ref source impedance 1.5 k external reference ref input voltage range v ref (note 9) 1 v dd v ref input current i ref f sample = 94.4ksps 40 ? digital inputs/outputs (scl, sda, a 0 ) input high voltage v ih 0.7 x v dd v input low voltage v il 0.3 x v dd v input hysteresis v hyst 0.1 x v dd v input current i in 10 ? input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v int output output low voltage i sink = 3ma 0.4 v int leakage current no faults detected ?0 a output capacitance 15 pf power requirements max1363 2.7 3.6 supply voltage v dd max1364 4.5 5.5 v downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 4 _______________________________________________________________________________________ electrical characteristics (continued)(v dd = 2.7v to 3.6v (max1363), v dd = 4.5v to 5.5v (max1364), v ref = 2.048v (max1363), v ref = 4.096v (max1364), c ref = 0.1?, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units internal reference 660 1600 f sample = 133ksps,monitor mode (note 10) external reference 436 1350 internal reference 900 1150 f sample = 94.4ksps,external clock external reference 670 900 internal reference 530 f sample = 40ksps,internal clock external reference 230 internal reference 380 f sample = 10ksps,internal clock external reference 60 internal reference 330 max1363 f sample = 1ksps,internal clock external reference 6 internal reference 660 1600 f sample = 133ksps,monitor mode (note10) external reference 436 1350 internal reference 900 1150 f sample = 94.4ksps,external clock external reference 670 900 internal reference 530 f sample = 40ksps,internal clock external reference 230 internal reference 380 f sample = 10ksps,internal clock external reference 60 internal reference 330 supply current i dd max1364 f sample = 1ksps, internalclock external reference 6 ? internal reference on 333 shutdown current internal reference off 0.5 10 ? power-supply rejection ratio psrr full-scale input (note 11) 0.01 0.5 lsb/v timing characteristics for fast mode (figures 1a, 2) serial clock frequency f scl 400 khz bus free time between astop (p) and a start (s) condition t buf 1.3 s downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response _______________________________________________________________________________________ 5 electrical characteristics (continued)(v dd = 2.7v to 3.6v (max1363), v dd = 4.5v to 5.5v (max1364), v ref = 2.048v (max1363), v ref = 4.096v (max1364), c ref = 0.1?, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units hold time for start (s) condition t hd , sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeatedstart condition (sr) t su , sta 0.6 s data hold time t hd , dat 0 900 ns data setup time t su , dat 100 ns rise time of both sda and sclsignals, receiving t r measured from 0.3v dd to 0.7v dd 0 300 ns fall time of sda transmitting t f measured from 0.3v dd to 0.7v dd 0 300 ns setup time for stop (p)condition t su , sto 0.6 s capacitive load for each busline c b 400 pf pulse width of spike suppressed 50 ns timing characteristics for high-speed mode (c b = 400pf, figures 1a, 2) (note 12) serial clock frequency f sclh (note 13) 1.7 mhz hold time, repeated start condition (sr) t hd , sta 160 ns low period of the scl clock t low (note 13) 320 ns high period of the scl clock t high 120 ns setup time for a repeatedstart condition (sr) t su , sta 160 ns data hold time t hd , dat (note 14) 0 150 ns data setup time t su , dat 10 ns rise time of scl signal, currentsource enabled t rcl measured from 0.3v dd to 0.7v dd 20 80 ns rise time of scl signal afteracknowledge bit t rcl1 measured from 0.3v dd to 0.7v dd 20 160 ns fall time of scl signal t fcl measured from 0.3v dd to 0.7v dd 20 80 ns rise time of sda signal t rda measured from 0.3v dd to 0.7v dd 20 160 ns fall time of sda signal t fda measured from 0.3v dd to 0.7v dd 20 160 ns setup time for stop (p)condition t su , sto 160 ns capacitive load for each busline c b (notes 13, 14) 400 pf pulse width of spike suppressed 0 10 ns downloaded from: http:///
typical operating characteristics (v dd = 3.3v (max1363), v dd = 5v (max1364), f scl = 1.7mhz, external clock, f sample = 94.4ksps, single-ended, unipolar, t a = +25?, unless otherwise noted.) max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 6 _______________________________________________________________________________________ electrical characteristics (continued)(v dd = 2.7v to 3.6v (max1363), v dd = 4.5v to 5.5v (max1364), v ref = 2.048v (max1363), v ref = 4.096v (max1364), c ref = 0.1?, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) note 1: devices configured for unipolar single-ended inputs. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset havebeen calibrated. note 3: offset nulled. note 4: conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.conversion time does not include acquisition time. scl is the conversion clock in the external clock mode. note 5: the throughput rate of the i 2 c bus is limited to 94.4ksps. the max1363/max1364 can perform conversions up to 133ksps in monitor mode when not reading back results on the i 2 c bus. note 6: a filter on the sda and scl inputs suppresses noise spikes and delays the sampling instant. note 7: the absolute input-voltage range for the analog inputs (ain0?in3) is from gnd to v dd . note 8: when the internal reference is configured to be available at ain3/ref (sel[2:1] = 11), decouple ain3/ref to gnd with a0.01? capacitor. note 9: adc performance is limited by the converter? noise floor, typically 300? p-p . note 10: maximum conversion throughput in internal clock mode when the data is not clocked out. note 11: for the max1363, psrr is measured as and for the max1364, psrr is measured as note 12: c b = total capacitance of one bus line in pf. note 13: f sclh must meet the minimum clock low time plus the rise/fall times. note 14: a master device must provide a data hold time for sda (referred to v il of scl) to bridge the undefined region of scl? falling edge. vvvv v vv fs fs n ref (. ) (. ) ( .. ) 55 45 21 55 45 [] ? ? ? ? ? ? ? ? vvvv v vv fs fs n ref (. ) (. ) (. . ) 36 27 21 36 27 [] ? ? ? ? ? ? ? ? -180 -160 -140 -120 -100 -80 -60 0 1 02 03 04 05 0 fft plot max1363/64 toc03 frequency (khz) amplitude (dbc) f sample = 94.4ksps f in = 10khz -0.5 -0.2 -0.4 -0.3 0.2 0.1 -0.1 0 0.3 0.5 0 4000 differential nonlinearity vs. digital code max1363/64 toc01 digital output code dnl (lsb) 1000 1500 500 2000 2500 3000 3500 0.4 -1.0 -0.4-0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 integral nonlinearity vs. digital code max1363/64 toc02 digital output code inl (lsb) 0 4000 1000 1500 500 2000 2500 3000 3500 downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response _______________________________________________________________________________________ 7 300 400350 500450 600550 650 750700 800 -40 -10 5 -25 20 35 50 65 80 supply current vs. temperature max1363/64 toc04 temperature ( c) supply current ( a) internal reference max1364 max1363 max1364 max1363 internal reference external reference external reference setup byteext ref: 10111010 int ref: 11011010 0 0.20.1 0.40.3 0.5 0.6 2.7 5.2 shutdown supply current vs. supply voltage max1363/64 toc05 input voltage (v) i dd ( a) 3.7 3.2 4.2 4.7 sda = scl = v dd 0 0.100.05 0.200.15 0.300.25 0.35 0.450.40 0.50 -40 -10 5 -25 20 35 50 65 80 shutdown supply current vs. temperature max1363/64 toc06 temperature ( c) supply current ( a) max1364 max1363 200 300250 350 400 450 500 550 600 650 700 750 800 0 20 30 40 60 80 100 average supply current vs. conversion rate (external clock) max1363/64 toc07 conversion rate (ksps) average i dd ( a) 010 50 70 90 a b a) internal reference always onb) external reference 0.9990 0.99940.9992 0.99980.9996 1.00021.0000 1.0004 1.00081.0006 1.0010 -40 -10 5 -25 20 35 50 65 80 internal reference voltage vs. temperature max1363/64 toc08 temperature ( c) v ref normalized max1364 max1363 normalized to reference value at +25 c 0.99990 0.999940.99992 0.999980.99996 1.000021.00000 1.00004 1.000081.00006 1.00010 2.7 3.3 3.6 3.9 3.0 4.2 4.5 4.8 5.1 5.4 normalized reference voltage vs. supply voltage max1363/64 toc09 v dd (v) v ref normalized max1364normalized to reference value at v dd = 5v max1363normalized to reference value at v dd = 3.3v -1.0 -0.8-0.9 -0.6-0.7 -0.4-0.5 -0.3 -0.1-0.2 0 -40 -10 5 -25 2035 506580 offset error vs. temperature max1363/64 toc10 temperature ( c) offset error (lsb) -1.0 -0.8-0.9 -0.6-0.7 -0.4-0.5 -0.3 -0.1-0.2 0 2.7 3.3 3.6 3.9 3.0 4.2 4.5 4.8 5.1 5.4 offset error vs. supply voltage max1363/64 toc11 v dd (v) offset error (lsb) typical operating characteristics (continued) (v dd = 3.3v (max1363), v dd = 5v (max1364), f scl = 1.7mhz, external clock, f sample = 94.4ksps, single-ended, unipolar, t a = +25?, unless otherwise noted.) 0 0.20.1 0.40.3 0.60.5 0.7 0.90.8 1.0 -40 -10 5 -25 20 35 50 65 80 gain error vs. temperature max1363/64 toc12 temperature ( c) gain error (lsb) downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 8 _______________________________________________________________________________________ pin name function 1 ain0 analog input 2 ain1 analog input 3 ain2 analog input 4a i n 3 / v ref analog input or reference input or output. see table 3. 5a 0 i 2 c address select input. connect to v dd or gnd. see table 1. 6 int active-low, open-drain interrupt output 7s c l i 2 c clock input 8 sda i 2 c data input/output 9 gnd ground 10 v dd positive supply voltage. bypass v dd to gnd with a 0.1? capacitor. pin description max1363/max1364 12-bit adc 4:1 mux control trip thresholds i 2 c interface sdascl a0 int clk int ref gnd v dd ain0ain1 ain2 ain3/ ref functional diagram 0 0.30.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.7 3.7 3.2 4.2 4.7 5.2 gain error vs. supply voltage max1363/64 toc13 v dd (v) gain error (lsb) monitor-mode supply current vs. speed max1363/64 toc14 speed (ksps) supply current ( a) 125 100 75 50 25 100 200 300 400 500 600 700 0 0 150 internal ref external ref typical operating characteristics (continued) (v dd = 3.3v (max1363), v dd = 5v (max1364), f scl = 1.7mhz, external clock, f sample = 94.4ksps, single-ended, unipolar, t a = +25?, unless otherwise noted.) downloaded from: http:///
detailed description the max1363/max1364 4-channel adcs use succes-sive-approximation conversion techniques and fully dif- ferential input track/hold (t/h) circuitry to capture and convert analog signals to a serial 12-bit digital output. the max1363/max1364 feature a monitor mode with programmable trip thresholds and window comparator. the monitor function asserts an interrupt when any channel violates the programmed upper or lower thresholds. smbus alert response allows the host microcontroller (?) to quickly identify which device caused the interrupt. a programmable delay between monitoring intervals lowers power consumption at lower monitor rates. the max1363/max1364 integrate an internal voltage reference and clock. the software configures the ana- log inputs for unipolar/bipolar and single-ended/fully differential operation. integrated first-in/first-out (fifo) allows conversion of all channels, or eight conversions on a selected channel to reduce interface overhead. ani 2 c-compatible serial interface complies with standard, fast, and high-speed (1.7mhz) modes. max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response _______________________________________________________________________________________ 9 t su.sta t su.dat t high t r t f t hd.dat t hd.sta s sr ack 9 scl sda t su.sta t low t buf t su.sto ps t r t f figure 1a. f/s-mode 2-wire serial-interface timing v dd i ol i oh v out 400pf sda figure 2. load circuits t hd.sta t su.dat t high t fcl t hd.dat t hd.sta sr sr ack scl sda t su.sta t low t su.sto s t rcl t rcl1 hs-mode 1 9 f/s-mode t fda t rda p figure 1b. hs-mode 2-wire serial-interface timing downloaded from: http:///
max1363/max1364 power supply the max1363 (2.7v to 3.6v) and max1364 (4.5v to5.5v) operate from a single supply and consume 670? (typ) at sampling rates up to 94.4ksps and 436? in monitor mode at 133ksps. the max1363 features a 2.048v internal reference, and the max1364 features a 4.096v internal reference. all devices can be configured for use with an external reference from 1v to v dd . bypass v dd to gnd using a 0.1? or greater ceramic capacitor for best performance. analog-input and track/hold the max1363/max1364 analog-input architecture con-tains an analog-input multiplexer (mux), fully differential t/h, comparator, and a fully differential switched capacitive digital-to-analog converter (dac). figure 3 shows the equivalent input circuit for the max1363/ max1364. in single-ended mode, the analog-input mux connects c t/h between the analog input selected by cs[3:0] and gnd (see the configuration/setup bytes (write cycle) section). in differential mode, the analog-input muxconnects c t/h to the plus and minus analog inputs selected by cs[3:0].during the acquisition interval, the t/h switches are in the track position, and c t/h charges to the analog-input signal. at the end of the acquisition interval, the t/hswitches move to the hold position, retaining the charge on c t/h as a stable sample of the input signal. during the conversion, a switched capacitive dacadjusts to restore the comparator input voltage to 0v within the limits of 12-bit resolution. this action requires 12 conversion clock cycles and is equivalent to trans-ferring a charge of 11pf x (v in + - v in -) from c t/h to the binary-weighted capacitive dac, forming a digital rep-resentation of the analog-input signal. use a low source impedance to ensure an accurate sample. a source impedance of up to 1.5k does not significantly degrade sampling accuracy. for largersource impedances, connect a 100pf capacitor from the analog input to gnd or buffer the input. in internal clock mode, the t/h circuitry enters track mode on the eighth rising clock edge of the address byte (see the slave address section). the t/h circuitry enters hold mode on the falling clock edge of theacknowledge bit of the address byte (the ninth clock pulse). the conversions are then internally clocked, dur- ing which time the max1363/max1364 hold scl low. in external clock mode, the t/h circuitry enters track mode after a valid address on the rising edge of the clock during the read bit (r/ w = 1). hold mode is entered on the rising edge of the second clock pulseduring the shifting out of the 1st byte of the result. the next 12 clock cycles perform the conversions. the time required for the t/h circuitry to acquire an input signal is a function of the input sample capaci- tance. if the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the minimum time needed for the signal to be acquired. it is calculated by: t acq 9 x (r source + r in ) x c in 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 10 ______________________________________________________________________________________ t r a c k tr a c k h o ld c t/h c t/h t r a c k tr a c k h o l d ain0 ain1 ain2 ain3/ref gnd analog-input mux capacitive dac ref capacitive dac ref max1363max1364 h o l d h o ld tr a c k h o l d v dd /2 figure 3. equivalent input circuit downloaded from: http:///
where r source is the analog-input source impedance, r in = 2.5k , and c in = 22pf. for internal clock mode, t acq = 1.5 / f scl , and for external clock mode t acq = 2 / f scl . analog-input bandwidth the max1363/max1364 feature input-tracking circuitrywith a 5mhz small-signal bandwidth. the 5mhz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre- quency signals from aliasing into the frequency band of interest, use anti-aliasing filtering. analog-input range and protection internal protection diodes clamp the analog inputs to v dd and gnd. these diodes allow the analog inputs to swingfrom (gnd - 0.3v) to (v dd + 0.3v) without causing dam- age to the device. for accurate conversions, the inputsmust remain within 50mv below gnd or above v dd . single-ended/differential input the se/ dif of the configuration byte configures the max1363/max1364 analog-input circuitry for single-ended or differential input. in single-ended mode (se/ dif = 1), the digital conversion results are the differencebetween the analog input selected by cs[3:0] and gnd. in differential mode (se/ dif = 0), the digital conversion results are the difference between the plus and the minusanalog inputs selected by cs[3:0] (see tables 5 and 6). unipolar/bipolar unipolar mode sets the differential input range from 0 tov ref . a negative differential analog input in unipolar mode causes the digital output code to be zero.selecting bipolar mode sets the differential input range to ? ref / 2. the digital output code is binary in unipo- lar mode and two? complement in bipolar mode. (seethe transfer functions section.) in single-ended mode the max1363/max1364 alwaysoperate in unipolar mode. the analog inputs are inter- nally referenced to gnd with a full-scale input range from 0 to v ref (table 7). reference sel[2:0] of the setup byte controls the reference andthe ain3/ref configuration. when ain3/ref is config- ured as a reference input or reference output (sel1 = 1), differential conversions on ain3/ref appear as if ain3/ref is connected to gnd. a single-ended conver- sion in scan mode on ain3/ref is ignored by an internal limiter that sets the highest available channel at ain2. internal reference the internal reference is 2.048v for the max1363 and4.096v for the max1364. sel1 of the setup byte con- trols whether ain3/ref is used for an analog input or a reference. decouple ain3/ref to gnd with a 0.1? capacitor and a 2k resistor in series with the capaci- tor. when ain3/ref is configured as an internal refer-ence output (sel[1:0] = 11). see the typical operating circuit . once powered up, the reference remains on until reconfigured. do not use the reference to supplycurrent for external circuitry. external reference the external reference ranges from 1v to v dd . for max- imum conversion accuracy, the reference must deliver40? and have an impedance of 500 or less. for noisy or high-output-impedance references, insert a0.1? bypass capacitor to gnd as close to ain3/ref as possible. clock modes the clock mode determines the conversion clock andthe data acquisition and conversion time. the clock mode also affects the scan mode. the state of the setup byte? int /ext clock bit determines the clock mode. at power-up, the max1363/max1364 default tointernal clock mode ( int /ext clock = 0). internal clock see the configuration/setup bytes (write cycle) section. in internal clock mode (clk = 0), the max1363/max1364 use an internal oscillator for the conversion clock. the max1363/max1364 begin tracking the analog input after a valid address on the eighth rising edge of the clock. on the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. while con- verting, the max1363/max1364 hold scl low (clock stretching). after completing the conversion, the results are stored in internal memory. for scan-mode configura- tions with multiple conversions (see the scan modes sec- tion), all conversions happen in succession with eachadditional result stored in memory. once all conversions are complete, the max1363/max1364 release scl, allowing it to go high. the master can now clock the results out in the same order as the scan conversion. the converted results are read back in a fifo sequence. if ain3/ref is configured as a reference input or output, ain3/ref is excluded from multichan- nel scan. if reading continues past the final result stored in memory, the pointer wraps around and points to the first result. only the current conversion results are read from memory. the max1363/max1364 must be addressed with a read command to obtain new conver- sion results. max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 11 downloaded from: http:///
max1363/max1364 external clock see the configuration/setup bytes (write cycle) section. when configured for external clock mode (clk = 1), themax1363/max1364 use scl as the conversion clock. in external clock mode, the max1363/max1364 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. two scl clock cycles later, the analog signal is acquired and the conversion begins. unlike internal clock mode, converted data is clocked out immediately in the format described in the reading a conversion (read cycle) section. the device continuously converts input channels dictat-ed by the scan mode until given a not acknowledge (nack). there is no need to readdress the device with a read command to obtain new conversion results. the conversion must complete in 1ms or droop on the t/h capacitor degrades conversion results. use internal clock mode if the scl clock period exceeds 60?. use external clock mode for conversion rates from 40ksps to 94.4ksps. use internal clock mode for conver- sions under 40ksps. internal clock mode consumes less power. monitor mode always uses internal clock mode. applications section power-on reset the configuration and setup registers default to a sin-gle-ended, unipolar, single-channel conversion on ain0 using the internal clock with v dd as the reference and ain3/ref configured as an analog input. the memorycontents are unknown at power-up (see the software description section). i 2 c-compatible 2-wire serial interface the max1363/max1364 use an i 2 c-compatible 2-wire interface consisting of a serial data line (sda) and serialclock line (scl). sda and scl facilitate bidirectional communication between the max1363/max1364 and the master at rates up to 1.7mhz. the master (typically a ?) initiates data transfer on the bus and generates the scl signal to permit data transfer. the max1363/ max1364 behave as i 2 c slave devices that transfer and receive data.sda and scl must be pulled high for proper i 2 c opera- tion. this is typically done with pullup resistors (750 or greater). series resistors (r s ) are optional (see the typical operating circuit section). the resistors protect the input architecture of the max1363/max1364 fromhigh voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. one bit transfers during each scl clock cycle. a mini- mum of nine clock cycles is required to transfer a byte in or out of the max1363/max1364 (8 bits and anack/nack). the data on sda must remain stable dur- ing the high period of the scl clock pulse. changes in sda while scl is stable and high are considered con- trol signals (see the start and stop conditions sec- tion). both sda and scl remain high when the bus isnot busy. start and stop conditions the master initiates a transmission with a start condi-tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high (figure 4). a repeated start condition (sr) can be used in place of a stop condition to leave the bus active and the mode unchanged (see the hs i 2 c mode section). acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit(ack) or a not-acknowledge bit (nack). both the mas- ter and the max1363/max1364 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 5). to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 12 ______________________________________________________________________________________ scl sda sp sr figure 4. start and stop conditions scl sda s not acknowledge acknowledge 12 89 figure 5. acknowledge bits downloaded from: http:///
unsuccessful data transfers. an unsuccessful data trans-fer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master reattempts communication at a later time. slave address the max1363/max1364 have a 7-bit i 2 c slave address. the slave address is selected using a0. themax1363/max1364 (eub, meub, and leub) have three base address options, allowing up to six devices concurrently per i 2 c bus (see table 1). the max1363/max1364 continuously wait for a startcondition followed by its slave address. when the device recognizes its slave address, it is ready to accept or send data depending on the r/ w bit (figure 6). hs i 2 c mode at power-up, the max1363/max1364 bus timing is setfor fast mode (f/s mode, up to 400khz i 2 c clock), which limits the conversion rate to approximately 22ksps.switch to high-speed mode (hs mode, up to 1.7mhz i 2 c clock) to achieve conversion rates up to 94.4ksps. the max1363/max1364 convert up to 133ksps in moni-tor mode, regardless of i 2 c mode. if conversion results are unread, i 2 c bandwidth limitations do not apply (see the monitor mode section). select hs mode by addressing all devices on the buswith the hs-mode master code 0000 1xxx (x = don? care). after successfully receiving the hs-mode master code, the max1363/max1364 issue a nack, allowing sda to be pulled high for one clock cycle (figure 7). after the nack, the max1363/max1364 operate in hs mode. send a repeated start (sr) followed by a slave address to initiate hs-mode communication. if the mas- ter generates a stop condition, the max1363/ max1364 return to f/s mode. use a repeated start condition (sr) in place of a stop condition to leave the bus active and the mode unchanged. max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 13 01 1 1 00 0 r / w ack slave address s scl sda 123456789 figure 6. max1363/max1364 slave address byte a0 state suffix address low eub 0110100 high eub 0110101 low meub 0110110 high meub 0110111 table 1. i 2 c slave selection table 000 1 0x x x nack hs-mode master code scl sda s sr f/s mode hs mode figure 7. f/s-mode to hs-mode transfer downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 14 ______________________________________________________________________________________ start condition start address from the master configuration byte from the master setup byte from the master 0 a a a stop r/w bit from the master figure 8. example of writing setup and control bytes start condition start address from the master setup byte from the master alarm reset, scan speed, byte from master 0a 1a a ch 0 lt [11:4] byte ch 0 lt [3:0]; ut [11:8] byte ch 1 lt [11:4] byte ch 0 ut [7:0] byte aaaa stop r/w bit from the master figure 9. example of extended setup byte writing bit name description 7(msb) config the configuration byte always starts with 0. 6 scan1 5 scan0 scan1, scan0 = [0,0], scans from channel 0 to the upper channel chosen by cs1, cs0.scan1, scan0 = [0,1], converts a single channel chosen by cs1, cs0 eight times. scan1, scan0 = [1,0] monitor mode monitors from channel 0 to the upper channel chosen by cs1, cs0. scan1, scan0 = [1,1], single channel conversion for the channel is chosen by cs0, cs1. 4c s 3 3c s 2 cs3, cs2 = [1,1] enables readback of monitor-mode setup data. 2c s 1 1c s 0 selects the upper limit of the channel range used for the conversion sequence in scan modes scan = [0,0]and monitor modes scan = [1,0]. selects the conversion channel when scan = [0,1] or when scan = [1,1]. (tables 5 and 6) 0 se/ dif 1 = single-ended inputs.0 = differential inputs. ain0 and ain1 form the first differential pair and ain2 and ain3 form the second differential pair. (see tables 4 and 5.) selects single-ended or differential conversions. in single-ended mode, input-signal voltages are referenced to gnd. in differential mode, the voltage difference between two channels is measured. when single-ended mode is used, the max1363/max1364 perform unipolar conversions regardless of the uni /bip bit in the setup byte. (table 7) table 2. configuration byte format** power-on defaults: 0x01 downloaded from: http:///
software description configuration/setup bytes (write cycle) a write cycle begins with the bus master issuing astart condition followed by 7 address bits and a write bit (r/ w = 0). if the address byte is successfully received, the max1363/max1364 (slave) issue an ack.the master then writes to the slave. if the most signifi- cant bit (msb) is 1, the slave recognizes the received byte as the setup byte (table 4). if the msb is 0, the slave recognizes that byte as the configuration byte (table 2). write to the configuration byte before writing to the setup byte (figure 8). if enabling reset in the setup byte, rewrite the configuration byte after writingthe setup byte, since reset clears the contents of the configuration byte back to the power-up state.when the monitor-setup bit of the setup byte is set to 1, writing extends up to 13 bytes to clock in monitor-setup data. terminate writing monitor-setup data at any time by issuing a stop or repeated start condition. if the slave receives a byte successfully, it issues an ack (figure 9). note: when operating in hs mode, a stop condition returns the bus into f/s mode (see the hs i 2 c mode section). automatic shutdown autoshutdown occurs between conversions when themax1363/max1364 are idle. when operating in exter- nal clock mode, issue a stop, nack, or repeated start condition to place the devices in idle mode and benefit from automatic shutdown. a stop condition is not necessary in internal clock mode for automatic shutdown because power-down occurs once all con- tents are written memory. shutdown reduces supply current to less than 0.5? (external reference mode, typ) and 300? (internal reference mode, typ). when idle, the max1363/max1364 continuously wait for a start condition followed by their slave address. upon reading a valid address byte, the max1363/ max1364 power up. the internal reference requires 10ms to wake up. therefore, power up the internal ref-erence 10ms prior to conversion or leave the reference continuously powered. wake-up is transparent when using an external reference or v dd as the reference. automatic shutdown results in dramatic power savings,particularly at slow conversion rates with internal clock. for example, using an external reference at a conver- sion rate of 10ksps, the average supply current for the max1363 is 60? (typ) and drops to 6? (typ) at 1ksps. at 0.1ksps, the average supply current is just 1?. table 3 shows ain3/ref configuration and refer- ence power-down state. scan modes scan1 and scan0 of the configuration byte set thescan-mode configuration. when configuring ain3/ref for reference input or output (sel0 = 1), ain3/ref is excluded from a multichannel scan. the scanned results write to memory in the same order as the con- version. start a conversion sequence by initiating a read with the desired scan mode. read the results from memory in the order they were converted (see the reading a conversion (read cycle) section). selecting channel scan mode [0,0] starts convertingfrom channel 0 up to the channel chosen by cs1, cs0. selecting channel scan mode [0,1] converts the chan- nel selected by cs1, cs0 eight times and returns eight consecutive results. selecting monitor mode [1,0] initiates a continuous con- version scan sequence from channel 0 to the channel selected by cs1, cs0. see the monitor mode section for more details.selecting channel scan mode [1,1] performs a single conversion on the channel selected by cs1, cs0 and returns the result. reading a conversion (read cycle) initiate a read cycle to start a conversion sequence andto obtain conversion results. see the scan modes section for details on the channel-scan sequence. read max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 15 sel1 sel0 int ref power-down reference voltage ain3/ref internal reference state 00 x v dd analog input always off 0 1 x external reference reference input always off 1 0 0 internal reference analog input always off 1 0 1 internal reference analog input always on 1 1 0 internal reference reference output always off 1 1 1 internal reference reference output always on table 3. reference voltage and ain3/ref format downloaded from: http:///
max1363/max1364 cycles begin with the bus master issuing a start condition followed by 7 address bits and a read bit (r/ w = 1). after successfully receiving the address byte, the max1363/max1364 (slave) issue an ack. the masterthen reads from the slave. (see figures 10?3.) the result is transmitted in 2 bytes. the 1st byte con- sists of a leading 1 followed by a 2-bit binary channel address tag, a 12/ 10 bit flag (1 for the max1363/ max1364), the first 4 bits of the data result, and theexpected ack from the master. the 2nd byte contains d7?0. to read the next conversion result, issue an ack. to stop reading, issue a nack. 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 16 ______________________________________________________________________________________ bit name description 7 (msb) setup setup byte always starts with 1. 6 ref/ain sel1 5 ref/ain sel0 when [0,0], ref/ain3 = ain3, ref = v dd. when [0,1], ref/ain3 = ref, apply external reference to ref.when [1,0], ref/ain3 = ain3, ref = internal reference. when [1,1], ref/ain3 = ref, ref = internal reference. (table 3) 4 int ref power down 1 = internal reference always powered up.0 = internal reference always powered down. (table 3) 3 int /ext clock 0 = internal clock.1 = external clock (max1363/max1364 use the scl clock for conversions). 2 uni /bip 0 = unipolar. 1 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, analog signal in 0 to v ref range can be converted. in differential bipolar mode, input signal can range from -v ref / 2 to +v ref / 2. when single-ended mode is chosen, the se/ dif bit of configuration byte overrides uni /bip, and conversions are performed in unipolar mode. 1 reset 1 = no action.0 = resets int and configuration register. setup register and channel trip thresholds are unaffected. 0 monitor setup 0 = no action.1 = extends writing up to 13 bytes (104 bits) of alarm reset mask. scans speed selection and alarm thresholds. see the configuring monitor mode section. table 4. setup-byte format** power-on defaults: 0x82 cs1 cs0 ch0 ch1 ch2 ch3 00+ 01 + 10 + 11 + table 5. channel selection in single-ended mode (se/ dif = 1) cs1 cs0 ch0 ch1 ch2 ch3 00+- 01 -+ 10 +- 11 -+ table 6. channel selection in differentialmode (se/ dif = 0) se/ dif uni /bip mode 0 0 differential inputs, unipolar 0 1 differential inputs, bipolar 1 0 single-ended inputs, unipolar 1 1 single-ended inputs, unipolar table 7. se/ dif and uni /bip table downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 17 high ch1 ch0 12/ 11 11 00 00 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 10 / 10 / 1 0 = 10b1 = 12b 0/1 0/1 0/1 0/1 ack 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ack/ nack table 8. data format start condition start address from the master 1, ch add, 10b/12b flag, result (4 msbs) result (8 lsbs) 1 ack ack ack stop r/w t acq t conv figure 10. example of reading the conversion result?xternal clock mode start address from the master max1363/max1364 keeps scl low result (8 lsbs) 1, ch add, 10b/12b, result (4 msbs) 1 ack ack ack stop t acq t conv 6.8 s max r/w figure 11. example of a single conversion using the internal clock, scan = 1,1 start max1363/max1364 keeps scl low address from the master 1ack ack ack t acq t conv t acq t conv conversion 1 6.8 s max conversion 2 max1363/max1364 keeps scl low 1, ch add, 10b/12b, result (4 msbs) result 1 (8 lsbs) stop ack ack 1, ch add, 10b/12b, result (4 msbs) result n (8 lsbs) t acq t conv conversion n r/w figure 12. example of scan-mode conversions using the internal clock, scan = 0,0 and 0,1 downloaded from: http:///
max1363/max1364 when the max1363/max1364 receive a nack, theyrelease sda allowing the master to generate a stop or a repeated start condition. monitor mode monitor-mode overview the max1363/max1364 automatically monitor up to fourinput channels. for systems with limited i 2 c bandwidth, monitor mode allows the ? to set a window by programming lower and upper thresholds during initial- ization, and only intervening if the max1363/max1364 detect an alarm condition. this allows an interrupt-driven approach as an alternative to continuously polling the adc with the ?. monitor mode reduces processor over- head and conserves i 2 c bandwidth. the following shows an example of events in monitor mode: 1) fault condition(s) detected, int asserted. 2) host ? services interrupt and sends smbus alert to identify the alarming device. the max1363/max1364 respond with the i 2 c slave address, pend- ing arbitration rules. (see the smbus alert section.) 3) the max1363/max1364 release the int . 4) host ? reads the alarm-status register, latched- fault register, and current-conversion results todetermine the alarming channel(s) and course of action. 5) host ? services alarm(s); adjusts system parame- ters as needed and/or adjusts lower and upperthresholds. 6) host ? resets the alarming channel. see the configuring monitor mode section. 7) monitor mode resumes. 8) if there is still an active fault, the device asserts int again. see step 1. writing scan1 and scan0 bits = [1,0] in the configura-tion byte activates monitor mode. the max1363/ max1364 scan from channels 0 up to the channel selected by [cs1:cs0] at a rate determined by the scan delay bits. the max1363/max1364 compare the conversion results with the lower and upper thresholds for each channel. when any conversion exceeds the threshold, the max1363/max1364 assert an interrupt by pulling int low (if enabled). the max1363/ max1364 set the corresponding flag bit in the alarm-status register and write conversion results to the latched-fault register to record the event causing the alarm condition. int active state is randomly delayed with respect to the conversion. depending on the number of channelsscanned and the position in the channel scan sequence, the maximum possible delay for asserting int is five con- version periods (37.5? typ, delay = 0,0,0). configuring monitor mode to write monitoring setup data, set the monitor-setup bit(bit 0 in setup byte) to 1 to extend writing up to 104 bits (13 bytes) of monitoring setup data. the number of bits written to the max1363/max1364 depends on whether the part is in single-ended or differential mode and whether the upper channel limit is set by [cs1:cs0] (table 9). terminate writing at any time by using a stop or repeated start condition. previous monitoring setup data not overwritten remains valid. a 1 written to the reset alarm ch_ clears the alarm, oth- erwise no action occurs (table 10). deassert int by 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 18 ______________________________________________________________________________________ ack ack 1, ch add, 10b/12b, result (4 msbs) result n (8 lsbs) t acq t acq conversion 1 t acq t acq conversion n start address from the master 1, ch add, 10b/12b result (4 msbs) result (8 lsbs) 1 ack ack ack figure 13. example of scan-mode conversions using the external clock, scan = 0,0 and 0,1 downloaded from: http:///
clearing all alarms or by initiating an smbus alert duringan alarm condition (see the smbus alert section). the delay 2, delay 1, delay 0 bits set the speed ofmonitoring by changing the delay between conver- sions. delay 2, 1, 0 = 000 sets the maximum possible speed; 001 divides the maximum speed by ~2. increasing delay values further divides the previous speed by two. int_en controls the open-drain int output. set int_en to 1 to enable the hardware interrupt. set int_en to 0to disable the hardware interrupt output. the int output tri-states when disabled or when there are no alarms.the master can also poll the alarm status register at any time to check the alarm status. repeat clocking channel threshold data up to the chan- nel programmed by cs1 and cs0 (table 12). for differ- ential input mode, omit odd channels; the lower and upper threshold data applies to channel pairs. there is no need to clock in dummy data for odd (or even) channels (table 6). to disable alarming on a specific channel, set the lower threshold to 0x800 and the upper threshold to 0x7ff for bipolar mode, or set the lower threshold to 0x000 and the upper threshold to 0xfff for unipolar mode. max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 19 alarm reset, scan speed, int_en , (8 bits) ain0 thresholds (24 bits) ain1 thresholds (skip if differential mode, or cs1, cs0 < 1) (24 bits) ain2 thresholds (skip if cs1, cs0 < 2) (24 bits) ain3 thresholds (skip if differential mode, or cs1, cs0 < 3) (24 bits) table 9. monitor-mode setup data format reset alarm ch 0 reset alarm ch 1 reset alarm ch 2 reset alarm ch 3 delay 2 delay 1 delay 0 int_en 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 table 10. alarm reset, scan speed register, and int_en data format delay 2 delay 1 delay 0 monitor-mode conversion rate (ksps) 0 0 0 133.0* 001 6 6 . 5 010 3 3 . 3 011 1 6 . 6 100 8 . 3 101 4 . 2 110 2 . 0 111 1 . 0 table 11. delay settings * when using delay = [0,0,0] in internal reference mode and ain3/ref configured as a ref output, the max1363/max1364 may exhibit a code-dependent gain error due to insufficient internal reference drive. gain error caused by this phenomenon is typically less than 1%fsr (0.1? c ref ) and increases with a larger c ref . avoid this gain error by using an external reference, v dd , as a reference or use an internal reference with ain3/ref as an analog input (see table 4). alternatively, choose delay bits other than [0,0,0] to lower the conversion rate. byte b7 b6 b5 b4 b3 b2 b1 b0 acknowledge 1 lt11 (msb) lt10 lt9 lt8 lt7 lt6 lt5 lt4 ack 2 lt3 lt2 lt1 lt0 (lsb) ut11 (msb) ut10 ut9 ut8 ack 3 ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 (lsb) ack table 12. lower and upper threshold data format x = don? care. ack = acknowledge. downloaded from: http:///
max1363/max1364 readback mode select readback mode by setting cs3, cs2 to [1,1] inthe configuration byte. begin a read operation to start reading back monitor-setup data. clock out delay bit settings, int_en bit, and the lower and upper thresh- olds programmed for each channel. readback mode follows exactly the same format as writing to the moni- tor-setup data, with the exception of the first 4 alarm- reset bits, which are always 1 (table 13). reading in monitor mode reading in monitor mode reads back the alarm-statusregister, latched-fault register, and current-conversion results as shown in table 14. the max1363/max1364 register pointer loops back to the beginning of the current-conversion result after reading the last conversion result. stop reading at any time by asserting a stop condition or nack. note: the max1363/max1364 do not update the cur- rent-conversion results register while reading in monitormode. monitor mode resumes after a stop condition or nack. alarm-status register and latched-fault register the latched-fault register records a snapshot of thealarming channel at the instance that a fault condition is asserted. an alarm-status bit of 1 (table 15) indicates a fault, and the data in the latched-fault register of the corresponding channel contains the conversion result that caused the alarm to trip. resetting alarms does not clear the latched-fault register, thus the latched-fault register contains valid data only if an alarm status bit is high for the given channel. the current-conversion register contains the most recent conversion results. if the user attempts to read past the last result of the current-conversion register, the max1363/max1364 wraps back to the beginning of the current-conversion result. the latched-fault register and current-conversion regis- ter follow the data format in the reading a conversion ( read cycle) section. register length depends on the number of conversions in one monitoring sequence.for example, when channel pairs 0/1 and channels 2/3 are monitored differentially, there are only two conver- sion results to report. the latched-fault register is 2 x 16 bits long, after which two current-conversion results fol- low. likewise, if cs0 and cs1 limit the upper bound of the channel scan range from ch0 to ch2 in single- ended mode, the latched-fault register clocks out 3 x 16 bits of data followed by the current-conversion results, also 3 x 16 bits. 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 20 ______________________________________________________________________________________ alarm reset/scan speed ain0 thresholds ain1 thresholds (skip if differential mode or cs1, cs0 < 1) ain2 thresholds (skip if cs1, cs0 < 2) ain3 thresholds (skip if differential mode or cs1, cs0 < 3) 1 1 1 1 d2 d1 d0 int 24 bits 24 bits 24 bits 24 bits table 13. readback-mode format alarm-status register latched-fault register current-conversion results 8 bits 16, 32, 48, or 64 bits 16, 32, 48, or 64 bits table 14. reading in monitor-mode data format ch0 up ch0 low ch1 up ch1 low ch2 up ch2 low ch3 up ch3 low 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 table 15. alarm-status register 0 = not-alarm condition. 1 = alarm condition. ain0 ain1 ain2 ain3 16-bit read 16-bit read 16-bit read 16-bit read table 16. latched-fault and current-conversion register downloaded from: http:///
resetting alarm reset alarms by writing to monitor-setup data. see the configuring monitor mode section and table 10. smbus alert the smbus-alert feature provides a quick method toidentify alarming devices on a shared interrupt. upon receiving an interrupt signal, the host ? can broadcast a receive byte request to the alert-response slave address (0001100). any slave device that generated an interrupt attempts to identify itself by putting its own address on the bus. the alert response can activate several different slave devices simultaneously. if more than one slave attempts to respond, bus arbitration rules apply, and the device with the lower address wins as a consequence of the open-collector bus. the losing device does not generate an acknowledgement and continues to hold the alert line low until serviced. successful reading of the alert response address de- asserts int . when the max1363/max1364 successfully send thei 2 c address, it can resume and reassert int right away (if the fault is still present). to prevent this from happen-ing, monitor mode does not resume until after the host controller resets the alarm in the alarm status register. any alarms not cleared when the device resumes moni- tor mode reassert int . transfer functions output data coding for the max1363/max1364 is bina-ry in unipolar mode and two? complement in bipolar mode with 1 lsb = v ref / 2 n , where n is the number of bits. code transitions occur halfway between succes-sive-integer lsb values. figures 14 and 15 show the transfer functions for unipolar and bipolar operations, respectively. layout, grounding, and bypassing only use pc boards. wire-wrap configurations are notrecommended since the layout should ensure proper separation of analog and digital traces. do not run ana- log and digital lines parallel to each other, and do not layout digital signal paths underneath the adc pack- age. use separate analog and digital pc board ground sections with only one star point (figure 16). high-frequency noise in the power supply (v dd ) could influence the proper operation of the adc? fast com-parator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1? and 4.7?, located asclose as possible to the max1363/max1364 power sup- ply. minimize capacitor lead length for best supply noise rejection. for extremely noisy supplies, add an attenua- tion resistor (5 ) in series with the power supply. max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 21 111...111 output code fs = ref + gndzs = gnd full-scale transition 111...110100...010 100...001 100...000 011...111 011...110 011...101 000...001 000...000 0 1 512 input voltage (lsb) (gnd) 1 lsb = v ref 1024 fs - 0.5 lsb figure 14. unipolar transfer function 011...111 output code zs = ain- 011...110000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 ain- input voltage (lsb) +fs - 1 lsb 1 lsb = v ref 1024 ain- v ref 2 fs = v ref + ain- 2 -fs = -v ref + ain- 2 -fs + 0.5 lsb figure 15. bipolar transfer function downloaded from: http:///
max1363/max1364 definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the valueson an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the max1363/max1364? inl is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when anactual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rmsquantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr (max)[db] = 6.02db x n + 1.76db in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of thefundamental input frequency? rms amplitude to rms equivalent of all other adc output signals. sinad(db) = 20 x log (signalrms / noiserms) effective number of bits effective number of bits (enob) indicates the globalaccuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the adc? full-scale range, calculate the enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rmssum of the input signal? first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest distortion component. thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log sinad db signal noise thd rms rms rms ( ) log = + ? ? ? ? ? ? ? ? 20 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 22 ______________________________________________________________________________________ gnd v logic = 3v/5v 3v or 5v supplies dgnd 3v/5v gnd *optional 4.7 f r* = 5 0.1 f v dd digital circuitry max1363max1364 figure 16. power-supply grounding connection downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response ______________________________________________________________________________________ 23 ordering information/selector guide (continued) part temp range pin-package i 2 c slave address supply voltage (v) max1364 eub+ -40? to +85? 10 ?ax 0110100/0110101 4.5 to 5.5 max1364meub+ -40? to +85? 10 ?ax 0110110/0110111 4.5 to 5.5 1 23 4 5 max 10 98 7 6 v dd gndsda scl ain3/v ref ain2 ain1 ain0 max1363max1364 top view a0 int pin configuration *optional *r s *r s analog inputs c sda scl gnd v dd sda scl ain0ain1 ain2ain3/ref 0.1 f c ref 0.1 f 2k r p r p r p 3v/5v 3v/5v 3v/5v max1363max1364 4.7 f int int typical operating circuit +denotes a lead-free package. downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response 24 ______________________________________________________________________________________ package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 10 ?ax u10c+4 21-0061 downloaded from: http:///
max1363/max1364 4-channel, 12-bit system monitors with programmable trip window and smbus alert response maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 2 3/07 corrected table 8 17 3 3/08 removed l grade from data sheet 1, 13, 23 downloaded from: http:///

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